About this previous year paper
BEC063 – CMOS DIGITAL DESIGN TECHNIQUE
Time: 3 Hours | Max Marks: 70
SECTION A – Short Answer Questions
(2 × 7 = 14 marks | Attempt ALL)
Write definition / formula + 1–2 key points
a. Wafer Preparation & Lithography in VLSI Fabrication
Wafer preparation: Conversion of pure silicon into polished wafers through crystal growth, slicing, and polishing.
Lithography: Process of transferring circuit patterns onto the wafer using photoresist and UV light.
b. Significance of Threshold Voltage (Vₜ) in MOSFET
Threshold voltage is the minimum gate-to-source voltage required to create a conducting channel.
It controls switching behavior, power consumption, and leakage current.
c. Enhancement vs Depletion MOSFET
| Enhancement MOSFET | Depletion MOSFET |
|---|---|
| Channel absent at VGS = 0 | Channel present at VGS = 0 |
| Needs gate voltage to turn ON | Can conduct without gate bias |
| Widely used in CMOS | Rarely used |
d. Transconductance (gₘ) in MOSFET
Transconductance is the rate of change of drain current with respect to gate voltage.
gm=dIDdVGSg_m = \frac{dI_D}{dV_{GS}}gm=dVGSdID
Higher gₘ ⇒ better amplification.
e. Lambda-Based Design Rules
Lambda (λ) rules express layout dimensions as multiples of λ (minimum feature size).
They simplify CMOS layout design and improve scalability and portability.
f. Propagation Delay of CMOS Inverter (Numerical)
Given:
C = 10 fF, R = 5 kΩ
tp=0.69RC=0.69×5k×10fFt_p = 0.69RC = 0.69 \times 5k \times 10fFtp=0.69RC=0.69×5k×10fF tp=34.5 pst_p = \mathbf{34.5\ ps}tp=34.5 ps
g. Function of Sense Amplifier in SRAM
A sense amplifier detects and amplifies small voltage differences on bit lines during read operation, enabling fast and reliable data access.
SECTION B – Medium Answer Questions
(7 × 3 = 21 marks | Attempt ANY THREE)
Write concept → explanation → diagram
a. CMOS n-Well Fabrication Process
Steps: n-well formation in p-substrate
Oxide growth Gate formation
Source & drain diffusion Metallization
Draw cross-sectional diagram for full marks.
b. Threshold Voltage Equation & Affecting Factors
VT=VT0+γ(ϕ+VSB−ϕ)V_T = V_{T0} + \gamma(\sqrt{\phi + V_{SB}} - \sqrt{\phi})VT=VT0+γ(ϕ+VSB−ϕ)
Affecting factors: Body bias
Oxide thickness Doping concentration
Temperature
c. CMOS Inverter & Voltage Transfer Characteristics (VTC)
Consists of PMOS + NMOS VTC shows switching behavior
Key parameters: VOH, VOL, VIH, VIL
Explain noise margin from VTC curve.
d. Pseudo-NMOS vs Transmission Gate Logic
| Pseudo-NMOS | Transmission Gate |
|---|---|
| Uses single PMOS load | Uses NMOS + PMOS |
| Static power dissipation | No static power |
| Simple design | Better performance |
e. Schmitt Trigger Circuit & Applications
A Schmitt trigger provides hysteresis, improving noise immunity.
Applications: Signal conditioning
Noise filtering Wave shaping
SECTION C – Attempt ANY ONE
(7 marks)
a. Second-Order Effects in MOSFET
DIBL: Threshold voltage reduction at high drain voltage
Channel Length Modulation (CLM): Increase in drain current with VDS
Body Effect: Increase in Vₜ due to substrate bias
These effects become significant in short-channel devices.
b. Scaling Effects in CMOS Technology
Power: Reduced voltage lowers power but leakage increases Speed: Smaller devices → faster switching
Density: More transistors per chip Explain constant field scaling.