About this previous year paper
This examination evaluates a student’s foundational and advanced understanding of digital circuits, Boolean algebra, combinational & sequential circuit design, logic families, and data converters (ADC/DAC).
The paper integrates both theoretical concepts and practical logic design skills required in computer engineering, embedded systems, and VLSI design.
It is divided into three sections to test conceptual clarity, analytical ability, circuit-design proficiency, and application-oriented knowledge.
SECTION A — Short Answer Questions (14 Marks)
(Seven questions × 2 marks each)
This section checks the student's core fundamentals of digital electronics.
1. Purpose of Binary Arithmetic
Emphasizes why all digital systems perform operations in binary form and how arithmetic supports processor and ALU operations.
2. Signed Magnitude Representation
Explains how positive and negative binary numbers are represented using a dedicated sign bit and magnitude bits.
3. Operation of a Multiplexer (MUX)
Describes how a MUX selects one input from multiple data lines based on select signals.
4. Difference Between Full Adder and Half Adder
Highlights that a half adder adds two bits, whereas a full adder adds three inputs (including carry-in).
5. Basic Building Blocks of Sequential Circuits
Flip-flops, latches, registers, counters, and clock-controlled elements.
6. Fan-Out in Logic Families
Shows how many inputs a single gate output can drive without performance loss.
7. Key Specifications of a DAC
Resolution, linearity, conversion time, settling time, accuracy, dynamic range, etc.
Section A ensures the student knows essential vocabulary and fundamental digital concepts.
SECTION B — Analytical / Design-Oriented Questions (21 Marks)
(Any three questions × 7 marks each)
This section evaluates the student’s ability to perform number conversions, design circuits, and explain device behavior.
1. Number System Conversions
Includes conversions between decimal, hexadecimal, octal, and binary.
Also requires expressing hex numbers A3Bₕ and 2F3ₕ in binary.
2. Full Adder Design
Construct truth table → derive Boolean expressions → simplify using algebra or K-map.
3. Flip-Flop Operations (SR, JK, D, T)
Covers behavior, characteristic equations, truth/excitation tables, advantages, and applications.
4. CMOS Inverter Design & VTC Curve
Draw CMOS inverter circuit → explain operation → switching threshold → noise margins → VTC graph.
5. Switched Capacitor Concept
Explains charge transfer, equivalent resistance, and applications in analog filters, ADCs, and sample-hold circuits.
Section B measures deep analytical understanding and practical circuit modeling ability.
SECTION C — Long Answer / Application Questions (35 Marks)
(One question chosen from each part)
PART 3 — Boolean Algebra & K-Maps
Option A – 4-Variable K-Map Simplification
Simplify:
F(A,B,C,D) = Σ(1,2,4,6,9,10,11,12,13,14,15)
Option B – Demorgan’s Theorem
State and prove:
(AB)′=A′+B′(AB)' = A' + B'(AB)′=A′+B′
(A+B)′=A′B′(A + B)' = A'B'(A+B)′=A′B′
These problems test Boolean logic manipulation and minimization proficiency.
PART 4 — Combinational Circuit Design
Option A – Full Adder Using NAND Gates
Uses universal NAND gates to implement SUM and CARRY logic.
Option B – 2-bit Magnitude Comparator
Design logic to compare two 2-bit numbers using Boolean expressions and circuit diagrams.
PART 5 — Sequential Logic Design
Option A – Mealy vs Moore Machines
Compares output dependency, state modeling, timing differences, and real-world applications.
Option B – Positive Edge Triggered D Flip-Flop
Circuit diagram → waveform explanation → setup time → hold time → edge sensitivity.
PART 6 — Logic Families & PLDs
Option A – TTL NAND Gate Specifications
Noise margin, propagation delay, power dissipation, fan-in, fan-out, and switching characteristics.
Option B – Programmable Logic Devices (PLDs)
Explains PROM, PLA, PAL, and how complex Boolean logic is implemented using programmable structures.
PART 7 — Data Converters (ADC/DAC)
Option A – R-2R Ladder DAC
Explains binary-weighted current division using R and 2R resistances.
Option B – Successive Approximation ADC (SAR ADC)
Covers internal DAC operation, comparator decision-making, SAR register steps, and timing sequence.