About this previous year paper
This question paper is from B.Tech Semester III – Computer Organization and Architecture (COA), Subject Code: KCS302, designed to assess the student's understanding of the internal structure, functioning, and design principles of computer systems. It thoroughly tests both theoretical concepts and problem-solving abilities, covering fundamentals of digital design, memory systems, CPU architecture, microprogramming, and data transfer techniques.
The paper is divided into three sections (A, B, C) and carries 100 marks, ensuring coverage of both basic and advanced concepts of COA.
SECTION A – Short & Direct Concept Questions (20 Marks)
This section contains 10 short questions (2 marks each), checking foundational clarity on:
Structural components of a computer
Horizontal vs vertical microprogramming
Register transfer statements with control functions
4-bit incremental circuit design
Daisy chaining vs centralized parallel arbitration
Magnetic tape transfer rate calculation
Arithmetic shift operations
Associative memory – advantages/disadvantages
Static RAM vs Dynamic RAM
Types of instruction formats
These questions ensure the student understands key definitions, architecture principles, and basic numerical computation.
SECTION B – Analytical & Technical Explanation Questions (30 Marks)
Students must attempt any three. These involve deeper understanding of digital hardware design, memory organization, and arithmetic operations.
Topics include:
Bus system design using multiplexers
Destination-initiated handshaking data transfer
2-bit × 2-bit array multiplier and divide operation flowchart
Complete cache mapping analysis (tag, index, block, word fields)
Address selection in control memory
These questions evaluate the student’s ability to analyze architecture, perform calculations, design circuits, and understand memory/caching mechanisms.
SECTION C – Long Answer / Problem-solving Questions (50 Marks)
This section has 5 questions; each question contains two choices.
Students must attempt one part from each.
Q3 – Floating Point Numbers / Booth’s Multiplication
Covers biased exponents, exponent arithmetic, and Booth’s multiplication algorithm.
Q4 – Bus System Design / Multiple Bus Organization
Diagram-based questions requiring understanding of CPU internal buses and multi-bus architecture.
Q5 – Address Mapping & Cache Writing Methods
Students must formulate logical & physical address formats or explain virtual-to-physical address mapping with cache write methods.
Q6 – CPU-IO Communication / Asynchronous Data Transfer
Includes block diagrams and method explanations like strobe control, handshaking, asynchronous transfer.
Q7 – Stack-based Expression Evaluation / Control Unit Operations
Covers stack machine instructions or comparison of hardwired vs microprogrammed control.
These questions measure the student’s mastery over CPU design, memory hierarchy, instruction execution, computational algorithms, and architectural diagrams.