(SEM-III) THEORY EXAMINATION 2019-20 DIGITAL SYSTEM DESIGN

This document is the B.Tech Semester III Theory Examination (2019–20) question paper for Digital System Design (KEC302) under Dr. A.P.J. Abdul Kalam Technical University (AKTU).
The uploaded file contains two pages, clearly divided into three sections: SECTION A, SECTION B, and SECTION C.
The exam is of 3 hours duration, with a total of 100 marks.

The paper tests fundamental and applied knowledge of Boolean algebra, multiplexers, subtractors, sequential circuits, FSM design, TTL/NAND gates, ADC basics, and logic family characteristics.

SECTION A — Short Questions (10 × 2 = 20 Marks)

(Page 1)

Section A contains ten 2-mark questions, each checking conceptual understanding of core digital electronics.

Based on Page 1, the questions include:

Solving the quadratic equation 7−11k+22=07 - 11k + 22 = 07−11k+22=0 and identifying the base of a number system

Simplifying Boolean expression using K-map

Constructing a half subtractor using logic gates

Designing a 4:1 multiplexer (using 2:1 MUX)

Meaning of race around condition in JK flip-flop

Difference between Latch vs. Flip-Flop

Logic families and their characteristics

Figure of merit and noise immunity of TTL & CMOS ICs

Advantages & disadvantages of flash-type ADC

Basic step of 9-bit DAC (output when 000000000 represents 0 volts)

All 10 questions are shown inside a table on Page 1 with marks and CO mapping.

SECTION B — Long Questions (Attempt Any 3 × 10 = 30 Marks)

(Page 1)

Section B contains five long descriptive questions, out of which students must attempt any three.

These questions include:

Designing a 4-bit parallel binary adder/subtractor

Designing a 4-bit comparator using logic gates

Discussing Mealy vs Moore FSM, defining excitation table

Designing a circuit for a given state diagram using T flip-flop

Explaining working & drawing of three-input TTL NAND gate

These questions require detailed explanation, logic diagrams, and FSM interpretation.

SECTION C — Advanced / Application-Based Questions (Q4–Q6)

(Page 2)

Section C contains three groups (Q4, Q5, Q6), each containing two alternatives (a or b).
The student must attempt one part from each question number, each carrying 10 marks.

Q4 — Binary Circuits

(a) Design a 4-bit parallel binary adder/subtractor
OR

(b) Design a 4-bit comparator using logic gates

Q5 — Finite State Machines

(a) Discuss Mealy and Moore FSM, concept of excitation table
OR

(b) Design circuit for the shown state diagram (Page 2 contains a clear FSM graph with states 00, 01, 10, 11 and labelled transitions)

Q6 — Logic Gates / TTL

(a) Draw and explain three-input TTL NAND gate
OR

(b) Explain operation of TTL NAND gate with diagram and internal working

Questions in Section C are fully aligned with the images and diagrams printed on Page 2.

OVERALL SUMMARY OF THE DOCUMENT

The Digital System Design paper evaluates a student's understanding of:

Boolean algebra & K-map simplification

Combinational circuits (MUX, comparator, subtractor)

Sequential circuits (flip-flops, race condition)

Logic families (TTL, CMOS)

ADC & DAC basics

FSM design (Mealy, Moore, state diagram conversion)

TTL NAND gate internals

Design and analysis of multi-bit circuits

The paper is structured according to AKTU standard pattern:

SECTION A: Short conceptual recall

SECTION B: Descriptive & design-based questions

SECTION C: Applied logic design & FSM problems

The uploaded file contains two pages, clearly formatted with tables, diagrams, and proper marks distribution.