About this previous year paper
Course: B.Tech (Electronics / Electrical / Computer Engineering)
Subject Code: EEC406
Subject Title: Introduction to Microprocessor
Exam Type: Theory
Duration: 3 Hours
Maximum Marks: 100
Academic Year: 2016–17
SECTION – A (10 × 2 = 20 Marks)
Short conceptual questions designed to test basic understanding.
| No. | Question | Key Concept Summary |
|---|---|---|
| (a) | What is a microprocessor? What technology is used? | A microprocessor is the CPU on a single IC chip that performs arithmetic, logic, and control operations. Modern processors use VLSI (Very Large Scale Integration) technology. |
| (b) | Different buses in a microprocessor. | - Address Bus: Carries address signals from processor to memory (unidirectional). - Data Bus: Transfers data between CPU and memory (bidirectional). - Control Bus: Carries control signals like RD, WR, IO/M. |
| (c) | Block Diagram of Microprocessor. | Includes ALU, Registers, Control Unit, Clock Generator, and Buses interconnected for instruction execution. |
| (d) | 8085 Address Capability (64 KB). | 8085 has a 16-bit address bus → 216=65,5362^{16} = 65,536216=65,536 memory locations (64 KB). |
| (e) | Number of instructions 8085 supports. | 8085 supports 74 basic instructions with 246 total opcodes. |
| (f) | Addressing Modes of 8085. | Immediate, Register, Direct, Indirect, and Implied modes. |
| (g) | Memory Segmentation in 8086. | Divides memory into segments (Code, Data, Stack, Extra) for modular access using segment registers. |
| (h) | 8085 Hardware Interrupts. | Five interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR. |
| (i) | I/O Port Access by 8085. | 8-bit port addressing → 256 I/O ports (00H–FFH). |
| (j) | Why A0–A7 and D0–D7 are multiplexed. | To minimize pin count; address and data share lines with timing control through ALE (Address Latch Enable). |
SECTION – B (5 × 10 = 50 Marks)
Descriptive and programming-based questions.
(a) Architecture of 8085
Functional Blocks: ALU, Registers (A, B, C, D, E, H, L), Program Counter, Stack Pointer, Flag Register, Instruction Register & Decoder, Timing & Control Unit.
Working: Executes instructions through fetch–decode–execute cycle.
(b) Interrupts in 8085
Hardware Interrupts: TRAP (non-maskable, highest priority), RST7.5, RST6.5, RST5.5, INTR.
Software Interrupts: RST0–RST7.
Masking: Enabled/disabled using SIM/RIM instructions.
(c) 8254 Programmable Interval Timer (PIT)
3 independent counters, 6 operating modes.
Used for time delay generation, baud rate control, event counting.
Functional blocks: Data Bus Buffer, Read/Write Logic, Control Word Register, Counters.
(d) I/O Mapped vs Memory-Mapped I/O
| Feature | I/O-Mapped I/O | Memory-Mapped I/O |
|---|---|---|
| Address Space | 8-bit | 16-bit |
| Instructions | IN, OUT | MOV, MVI, etc. |
| Address Lines | 256 ports | 64 KB memory space |
| Advantage | Simplified I/O control | Can use all data operations |
(e) Programmable Peripheral Interface (8255 PPI)
Ports: A, B, C (8-bit each).
Modes:
Mode 0: Simple I/O
Mode 1: Strobed I/O
Mode 2: Bidirectional
BSR (Bit Set/Reset) mode for Port C bit control.
Used for keyboards, displays, sensors.
(f) Assembly Program – Block Transfer
Ten 8-bit numbers from 2100H → 3100H
LXI H,2100H ; Source LXI D,3100H ; Destination MVI C,0AH ; Counter = 10 LOOP: MOV A,M STAX D INX H INX D DCR C JNZ LOOP HLT
(g) Software vs Hardware Interrupts
| Type | Triggered By | Examples |
|---|---|---|
| Hardware | External signal | TRAP, RST7.5, etc. |
| Software | Instructions | RST n |
(h) Addressing Modes of 8085
Immediate: MVI A, 55H
Register: MOV A, B
Direct: LDA 2500H
Indirect: MOV A, M
Implied: CMA
SECTION – C (2 × 15 = 30 Marks)
Analytical and detailed system-level questions.
Q3. 8086 Microprocessor Features & Architecture
Features: 16-bit processor, 20-bit address bus (1 MB memory), 14 registers, pipelined architecture.
Architecture: Divided into:
Bus Interface Unit (BIU): Fetches instructions, manages queue, handles segment registers.
Execution Unit (EU): Executes instructions, performs ALU operations.
Q4. 8251 USART (Serial Communication)
Converts parallel → serial & serial → parallel data.
Functional Blocks: Data Bus Buffer, Transmitter, Receiver, Modem Control, and Control Word Register.
Interfacing: Connects to 8086 through RD’, WR’, CS’, and address lines.
Used in serial devices (modems, RS-232).
Q5. 8257 DMA Controller
Direct Memory Access (DMA) allows peripheral to transfer data directly to memory.
Blocks: Data Bus Buffer, Read/Write Control Logic, Priority Resolver, and DMA Channels (0–3).
Working: CPU sends HOLD → DMA takes control → transfers → sends HLDA (acknowledge).
Summary
The EEC406 – Introduction to Microprocessor exam thoroughly evaluates:
8085/8086 architecture & operations
Instruction set and addressing modes
Peripheral interfacing (8251, 8254, 8255, 8257)
Programming (assembly-level logic)
Interrupt handling and bus systems