About this previous year paper
Subject Code: BEC058
Maximum Marks: 70
Time: 3 Hours
Paper ID: 310337
Question Paper Overview
SECTION A (2 × 7 = 14 Marks)
(Short conceptual and definition-based questions)
a. Define the threshold voltage of a MOSFET.
b. Describe the impact of short channel effects on MOSFET performance.
c. Explain the concept of a cascode current mirror.
d. What are the two main types of noise in CMOS circuits?
e. Why is flicker noise significant in low-frequency applications?
f. What is a folded cascode amplifier?
g. Explain the concept of pole-zero compensation.
SECTION B (Attempt any three × 7 = 21 Marks)
a. Explain the concept of short-channel effects in MOSFETs. How do they influence device behavior?
b. What is the Miller effect, and how does it impact the frequency response of amplifiers?
c. Explain the difference between thermal noise and flicker noise. Why is flicker noise more prominent at lower frequencies?
d. Explain the design principles of a one-stage CMOS operational amplifier. What are its key advantages and limitations compared to a two-stage op-amp?
e. Discuss the importance of Design Rule Check (DRC) in the layout process. How does it ensure reliability and manufacturability of ICs?
SECTION C (Attempt one part from each question × 7 = 35 Marks)
Q3
(a) Explain the differences between MOSFET Level 1 and Level 2 models.
OR
(b) Compare the operation of a common-source amplifier with a resistive load and a triode load.
Q4
(a) Explain the working principle of a basic current mirror and discuss its limitations.
OR
(b) Evaluate the impact of small-signal parameters on the performance of an active current mirror.
Q5
(a) Discuss how feedback affects loading effects and overall gain in amplifiers.
OR
(b) Explain the concept of feedback in amplifiers and describe the four basic feedback topologies.
Q6
(a) Explain the concept of gain boosting in operational amplifiers. How does it enhance the performance of low-gain stages?
OR
(b) Explain the architecture of a telescopic amplifier and its key features. Why is it often preferred in low-power applications?
Q7
(a) Explain the concept of stability in multi-stage operational amplifiers. How do phase margin and gain margin influence stability?
OR
(b) Derive the expression for phase margin of a three-stage operational amplifier and explain how it affects the transient response.
Key Topics for Revision
1. Threshold Voltage (Vth)
VTH=VFB+2ϕF+2qϵsiNA(2ϕF)/CoxV_{TH} = V_{FB} + 2\phi_F + \sqrt{2q\epsilon_{si}N_A(2\phi_F)}/C_{ox}VTH=VFB+2ϕF+2qϵsiNA(2ϕF)/Cox
Determines when MOSFET turns ON; affected by oxide thickness, doping, and body bias.
2. Short-Channel Effects (SCE)
Drain-Induced Barrier Lowering (DIBL): Reduces threshold voltage.
Velocity Saturation: Limits carrier velocity, reducing gain.
Hot Carrier Effects: Cause reliability degradation.
Mitigation: Lightly Doped Drain (LDD), scaling techniques.
3. Cascode Current Mirror
Combines two transistors for high output resistance and gain.
Reduces channel-length modulation.
Used in high-speed amplifiers and biasing circuits.
4. Types of Noise in CMOS
| Type | Origin | Frequency Dependence |
|---|---|---|
| Thermal Noise | Random motion of carriers | Constant (white noise) |
| Flicker (1/f) Noise | Carrier trapping/release at oxide interface | Dominant at low frequencies |
5. Folded Cascode Amplifier
Modified version of telescopic amplifier with folded current paths.
Allows larger output swing and improved input common-mode range.
Preferred for low-voltage design.
6. Pole-Zero Compensation
Used to improve phase margin and stability of multi-stage op-amps.
Adds a zero to cancel out a dominant pole.
Common method: Miller compensation using capacitor CcC_cCc.
7. Miller Effect
Feedback capacitance between input and output increases effective input capacitance.
Reduces bandwidth and speed of amplifier.
Compensation techniques: Miller neutralization, cascode configuration.
8. CMOS Op-Amp Design
| Type | Features | Application |
|---|---|---|
| One-Stage | Simple, high speed, low gain | Buffer or pre-amplifier |
| Two-Stage | High gain, large swing | Precision amplifiers |
9. Design Rule Check (DRC)
Verifies layout geometry against fabrication limits.
Checks spacing, width, overlap, and enclosure rules. Prevents shorts, opens, and yield loss.
10. MOSFET Models
| Model | Description |
|---|---|
| Level 1 | Simplified, ideal MOSFET (square-law) model |
| Level 2 | Includes short-channel effects, body effect, and channel-length modulation |
11. Feedback in Amplifiers
Purpose: Control gain, increase bandwidth, reduce distortion.
Types:
Voltage–Series (Series–Shunt) Voltage–Shunt (Shunt–Shunt)
Current–Series (Series–Series) Current–Shunt (Shunt–Series)
12. Gain Boosting
Adds auxiliary amplifier to increase effective gain of cascode stage.
Improves output resistance and DC gain without increasing complexity.
Used in low-voltage, low-power op-amps.
13. Telescopic Amplifier
Single-stage amplifier with stacked transistors.
Offers high gain, low noise, low power, but limited output swing.
Suitable for low-power analog front-ends.
14. Stability of Multi-Stage Amplifiers
Phase Margin (PM): Indicates damping — higher PM → stable system.
Gain Margin (GM): Indicates tolerance before oscillation.
Typical stable design: PM > 60°, GM > 10 dB.
Controlled via compensation capacitors and pole splitting.
15. Phase Margin Derivation
For a 3-stage op-amp:
PM=180°+∠A(jωc)βPM = 180° + \angle A(j\omega_c)\betaPM=180°+∠A(jωc)β
→ Determines overshoot and settling time.
Higher PM = smoother response; lower PM = oscillations.
Exam Preparation Tips
Revise MOSFET models, noise, and compensation methods thoroughly.
Draw cascode and current mirror diagrams clearly.
Practice numerical examples (e.g., DIBL, Miller effect, gain).
Understand layout verification (DRC/LVS) importance.