About this previous year paper
This subject focuses on Operational Amplifiers (Op-Amps), Analog and Digital Integrated Circuit Design, and applications of ICs like 741, 555 Timer, and PLL (Phase Locked Loop).
It bridges analog electronics and digital systems, helping students understand how real-time signal processing, amplifiers, filters, oscillators, and logic circuits are built using ICs.
Exam Details
Course: B.Tech (Semester V)
Subject Code: KEC501
Subject Title: Integrated Circuits
Exam Duration: 3 Hours
Maximum Marks: 100
Paper ID: 310217
Date: 16 January 2024
Pattern: 3 Sections (A, B, C)
Instruction: Attempt all sections. If any data is missing, assume suitable values
Paper Pattern Overview
| Section | Type of Questions | Questions | Marks | Focus Area |
|---|---|---|---|---|
| A | Short Answer | 10 | 20 | Basic concepts and definitions |
| B | Descriptive (Any 3) | 5 | 30 | Circuit explanation + numerical analysis |
| C | Analytical/Design (Any 1 part each) | 5 | 50 | Derivations, applications, design, and simulation |
SECTION A — Short Questions (10 × 2 = 20 Marks)
Each question carries 2 marks, focusing on fundamentals and quick recall.
(a) Device parameters for IC 741
Common parameters:
Input offset voltage: 1–5 mV
Input bias current: 80 nA
Slew rate: 0.5 V/µs
Gain bandwidth: 1 MHz
CMRR: 90 dB
Input impedance: 2 MΩ
Output impedance: 75 Ω
(b) Advantages of Widlar Current Mirror
Produces low bias currents using high resistors.
Improves current matching.
Reduces chip area in IC 741 design.
Provides temperature stability.
(c) Define 3-dB Points in Frequency Response
Frequencies at which output power falls to half (or voltage to 0.707 of mid-band value).
They define the bandwidth of an amplifier.
(d) Advantages of Instrumentation Amplifier
High input impedance, low output impedance.
High Common Mode Rejection Ratio (CMRR).
Accurate differential amplification.
Useful for sensor and biomedical signal conditioning.
(e) Voltage Comparator vs. Zero Crossing Detector
| Comparator | Zero Crossing Detector |
|---|---|
| Compares two arbitrary voltages. | Compares input with 0 V reference. |
| Output switches when V+ > V–. | Output switches when input crosses zero. |
| Reference adjustable. | Fixed reference at ground. |
(f) Analog Multiplier as Phase Detector
In PLL systems, multiplying two sinusoidal signals produces a DC component proportional to the phase difference → acts as a phase detector.
(g) Differentiate between PUN and PDN
| PUN (Pull-Up Network) | PDN (Pull-Down Network) |
|---|---|
| Built using PMOS transistors. | Built using NMOS transistors. |
| Connects output to VDD (logic 1). | Connects output to GND (logic 0). |
(h) Advantage of Master-Slave Flip-Flop
Eliminates race-around condition.
Master captures input on one clock edge; slave outputs on opposite edge → stable and synchronized operation.
(i) Define Voltage-Controlled Oscillator (VCO)
A circuit whose oscillation frequency varies with control voltage, e.g., IC 566. Used in PLLs and frequency modulators.
(j) Define Lock Range and Capture Range
Lock Range: Frequency range within which PLL remains locked once synchronized.
Capture Range: Frequency range within which PLL can acquire lock from an unlocked state.
SECTION B — Descriptive Questions (Any 3 × 10 = 30 Marks)
Each question expects derivations, circuit analysis, or waveform explanation.
Q2(a) DC Analysis of IC 741 Input Stage
Identify transistor pairs (Q1–Q4) forming differential amplifier.
Calculate bias currents, collector voltages, and tail current source.
Explain bias stabilization using current mirrors.
Q2(b) Generalized Impedance Converter (GIC):
A circuit using op-amps to simulate inductors, resistors, or capacitors electronically.
Derive impedance relation Z=Z1Z3Z5Z2Z4Z = \frac{Z_1 Z_3 Z_5}{Z_2 Z_4}Z=Z2Z4Z1Z3Z5.
Design to simulate 2 mH inductor.
Q2(c) Astable Multivibrator using Op-Amp:
Uses Schmitt Trigger + RC charging network.
Output toggles between +Vsat and –Vsat.
Frequency: f=12RCln1+β1−βf = \frac{1}{2 R C \ln{\frac{1+β}{1−β}}}f=2RCln1−β1+β1
Design for 5 kHz square wave generator.
Q2(d) D Flip-Flop using CMOS Inverter:
Implemented with transmission gates and cross-coupled inverters.
Master-Slave configuration ensures edge-triggering and eliminates glitches.
Q2(e) IC 566 (VCO):
Generates square and triangular waveforms.
Frequency expression: f=2.4(VCC−VC)RCVCCf = \frac{2.4(V_{CC} - V_C)}{R C V_{CC}}f=RCVCC2.4(VCC−VC).
Diagram shows internal current source and Schmitt trigger.
SECTION C — Analytical / Design Questions (Any 1 part per question = 50 Marks)
Q3(a)
Draw small-signal model of IC 741 and derive overall voltage gain Av=A1A2A3A_v = A_1 A_2 A_3Av=A1A2A3.
Includes differential amplifier (input), level shifter, and class AB output stage.
Q3(b)
Calculate small-signal resistance between node A & A′ (figure given in question) using transistor small-signal parameters rπ,β,ror_π, β, r_orπ,β,ro.
Q4(a)
Derive transfer functions of Low Pass, High Pass, and Band Pass Filters using KHN Universal Active Filter.
Given: Q = 25, f₀ = 2 kHz →
BW=f0Q=200025=80 HzBW = \frac{f_0}{Q} = \frac{2000}{25} = 80\,HzBW=Qf0=252000=80Hz
Q4(b)
List V–I and I–V converter properties, discuss:
Voltage-to-current converter with grounded load (simple op-amp circuit).
Floating load version using two op-amps.
Q5(a)
Discuss Logarithmic Amplifier:
Output ∝ log of input voltage,
Vo=Klog(ViIsR)V_o = K \log{\left(\frac{V_i}{I_s R}\right)}Vo=Klog(IsRVi)
Used for dB scaling and automatic gain control.
Include temperature compensation using matched diode pairs.
Q5(b)
Triangular Wave Generator:
Combination of an integrator and a Schmitt trigger.
Frequency:
f=14RfRiCln1+β1−βf = \frac{1}{4 R_f R_i C \ln{\frac{1+β}{1−β}}}f=4RfRiCln1−β1+β1
Q6(a)
Realization of Clocked SR Flip-Flop using CMOS inverter —
Built using transmission gates and NOR/NAND logic. Discuss edge-triggering behavior.
Q6(b)
Implement and verify logic using CMOS:
2-input NAND gate — PUN in parallel, PDN in series.
Y=ABC‾+DE‾Y = \overline{A B C} + \overline{D E}Y=ABC+DE —
Complex logic implementation using DeMorgan’s law.
Q7(a)
555 Timer as Astable Multivibrator:
RA=2.2kΩ,RB=3.9kΩ,C=0.01µFR_A = 2.2 kΩ, R_B = 3.9 kΩ, C = 0.01 µFRA=2.2kΩ,RB=3.9kΩ,C=0.01µF
Frequency: f=1.44(RA+2RB)Cf = \frac{1.44}{(R_A + 2R_B)C}f=(RA+2RB)C1.44
Duty Cycle: D=RA+RBRA+2RBD = \frac{R_A + R_B}{R_A + 2R_B}D=RA+2RBRA+RB
Q7(b)
Phase-Locked Loop (PLL):
Components: Phase detector, LPF, VCO, feedback loop.
Applications:
FM demodulation
Frequency synthesis
Clock recovery
Motor speed control
Key Topics to Revise Before Exam
Internal circuit of IC 741 and current mirrors.
Frequency response, 3-dB points, and gain-bandwidth product.
Astable and monostable configurations using Op-Amps or 555 timer.
KHN Filter derivation and frequency analysis.
VCO and PLL — operation, lock and capture range.
Logarithmic amplifier and temperature compensation.
CMOS logic design, PUN and PDN implementation.
Conclusion
The Integrated Circuits (KEC501) exam is designed to test a student’s conceptual understanding, analytical derivations, and practical circuit knowledge.
It covers the complete analog–digital interface, from IC 741 op-amp fundamentals to advanced design concepts like PLL, VCO, and CMOS-based logic circuits.
To score high:
Practice circuit diagrams and derivations.
Learn formulas for frequency, gain, and bandwidth.
Revise applications and temperature effects in real ICs.